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The synchronous buck converter uses voltagemode control with fast transient response. The output is user-adjustable by means of external resistors down to 0. Each output is monitored for undervoltage events. The switching regulator also has overvoltage and over current protection. Thermal shutdown is integrated. ACPI compliant sleep state control? Glitch-free Transitions During State Changes?
Under and Over-voltage Monitoring on All Outputs? OCP on the Switching Regulator? Integrated Thermal Shutdown Protection? Graphics cards – GPU and memory supplies? These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. All Rights Reserved All other trademarks mentioned are the property of their respective owners. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
See Tech Brief TB It is typically connected to the 5V standby rail of an ATX power supply. The supply to 5VSBY should be locally bypassed using a 0.
High ground currents are conducted directly through the exposed paddle of the QFN package which must be electrically connected to the ground plane through a path as low in inductance as possible.
An over-current trip cycles the soft-start function. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the upper MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. During S3 state, the VTT regulator is disabled. Connect this pin to the VTT output at the physical point of desired regulation.
This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the lower MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. It is recommended that a minimum capacitance of 0.
The minimum value for CSS can be found through the following equation: FB is the negative input to the voltage loop error amplifier. With a properly selected divider, VDDQ can be set to any voltage between the power rail reduced by converter losses and the 0. The FB pin is also monitored for under and over-voltage events. It is primarily designed for computer applications powered from an ATX power supply.
(PDF) AT9173 Datasheet download
A kHz Synchronous Buck Regulator with a precision 0. The voltage at this pin is regulated to 0. This pin is monitored for under-voltage events. Initialization The ISL automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary.
All references to timing in this section are in reference to Figure 1. This reset lasts for three soft start cycles, which is typically 24ms one soft start cycle is typically 8. The digital soft start sequence will then begin.
Each regulator is enabled and soft-started according to a preset sequence. To insure that both upper and lower pass transistors dissipate the same power, tie this pin to the VGMCH output rail. This method provides a rapid and controlled output voltage rise.
The error amplifier reference is clamped to the internal digital soft-start voltage. This allows the termination voltage to float during the S3 sleep state. This allows the VTT rail to float. It is important to note that the VTT rail may not bleed down to 0V. Figure 1 shows how the individual regulators are affected by the S3 state at time t7. This sequence is very similar to the mechanical start soft-start sequencing.
The transition from S3 to S0 is represented in Figure 1 between times t8 and t This enables the ATX, which brings up the 12V rail. At time t10, the 3 soft-start cycle reset is ended and the individual regulators are enabled and soft-started in the same sequence as the mechanical cold start sequence, with the exception that the VDDQ regulator is already enabled and in regulation.
This transition is represented on Figure 1 adtasheet time t The VDDQ regulator also has overcurrent protection. All other regulators are monitored for under-voltage events.
If a regulator experiences any other fault condition an under-voltage or an overcurrent on VDDQthen that regulator, and only that regulator, will be disabled and an internal fault counter will be incremented by 1.
If the disabled regulator is used as the input for another regulator, then that cascoded regulator will also experience a fault condition due to a loss of input. The cascoded regulator will be disabled and the fault counter adtasheet by catasheet. At every fault occurrence, the internal fault counter is incremented by 1 and an internal Fault Reset Counter is cleared to zero.
If the Fault Reset Counter reaches a count of before another fault occurs, then the Fault Counter is cleared to 0. If a fault occurs prior to the Fault Reset Counter reaching a count ofthen the Fault Reset Counter is set back to zero.
Datwsheet ISL will immediately shut down when the Fault Counter reaches a count of 4 when the system is restarting from an S5 state into the active, or S0, state. The counts that are required to reset the Fault Reset Counter represent 8 soft-start cycles, as one soft-start cycle is clock cycles.
This allows the ISL to attempt at least one full soft-start sequence to restart dxtasheet faulted regulators. When attempting to eatasheet a faulted regulator, the ISL will follow the preset start up sequencing. If a regulator is already in regulation, then it will not be affected by the start up sequencing. Shoot-Through Protection A shoot-through condition occurs when both the upper and lower MOSFETs are turned on simultaneously, effectively shorting the input voltage to ground. This method a9t173 the VDDQ regulator to both source and sink current.
Doing so may interfere with the shootthrough protection. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. The initiation of soft datasehet may affect other regulators. With power devices darasheet efficiently at kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress.
Careful component layout and printed circuit board design minimizes these voltage spikes. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL switching converter. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: The maximum rDS ON at the highest junction temperature.
I is the output inductor ripple current.
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Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. A multi-layer printed circuit board is recommended. Figure 2 shows the connections of the critical components in the converter. Dedicate one solid layer, usually a middle layer of the PC board, for a ground darasheet and make all critical component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes.
Use the remaining printed circuit layers for small signal wiring. In order to dissipate heat generated by the internal VTT LDO, the ground pad, pin 29, should be connected to the internal ground plane through at least a9173 vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL first. Minimize the length of the connections between the input capacitors, CIN, and the power switches by placing dwtasheet nearby.
The critical small signal components include any bypass capacitors, feedback components, and compensation components. The feedback resistors should be located as close as possible to the FB pin with vias tied straight to the ground plane as required. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6.
Using the above guidelines should give a Compensation Gain similar to the curve plotted.
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The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. This is equivalent to multiplying at913 modulator transfer function to the compensation transfer function and plotting the gain.
Include worst case component variations when determining phase margin.